1. Field of Invention
Invention relates to digital-to-analog converters (DACs) and more particularly to digital-to-analog converters with cascading segments.
2. Description of Related Art
DACs are presently available to produce an analog voltage output by selectively tapping a resistor string connected between the high voltage reference and ground or the low voltage reference. However, once the resolution of the DAC is over six or eight bits, the number of components required is fairly high. For example, a 10-bit DAC of this topology would require 1024 resistors, 1024 switches, and 1024 logic drive lines. A DAC design that does not require the high number of elements is desirable as the silicon area needed for the circuit would be reduced which in turn would lower manufacturing costs.
Several DAC architectures have concentrated on cascading segments where a first segment includes a resistor string that produces a first voltage corresponding to the most significant bits (MSB) and the second segment includes a resistor string that produces a voltage corresponding to the least significant bits (LSB). The second segment uses the output voltage of the first segment of the DAC such that the second segment effectively interpolates the selected first segment voltage to correspond with the LSB. One such device is described in U.S. Pat. No. 3,997,892.
Other prior art approaches for cascaded segment converters suffer from linearity problems and other performance characteristics when applied to higher resolution DACs. Thus, there is a need for a DAC architecture that reduces the number of circuit components while achieving satisfactory linearity characteristics.
Invention resides in a cascading DAC design that achieves the reduction of the number of circuit components and maintains good performance characteristics. The present invention includes a segmented DAC architecture where the first segment DAC processes N1 most significant bits of an N-Bit DAC and the subsequent segment DACs process the balance of the bits, (Nxe2x88x92N1), of the N-bit input digital signal. The DAC architecture includes ballast resistors that nullify the effect of any imbalance of the resistance on the first segment DAC versus the sum of the resistances in the remaining segment DACs.
One embodiment involves a two-segment cascading design for a 10-Bit DAC where the first segment processes the two MSB and the second segment processes the eight LSB. In one application of the present invention, two 10-Bit DACs, with their associated circuits comprising a 10-Bit volatile data latch, a 10-Bit nonvolatile data register, and a unity gain operational amplifier, are integrated with a configuration register and a standard two-wire serial interface.
The present invention may have a first segment that is a 2, 4, 6, 8 or higher bit DAC while the second or subsequent segments may be 2, 4, 6, 8, or higher bit DACs and the principles and approach of the architecture would apply.